QSYS BFM Simulation VHDL Help

Hi,

I have followed the tutorial QSYS Avalon-MM Master BFM Tutorial for SystemVerilog and VHDL Testbenches:

http://www.alteraforum.com/forum/showthread.php?t=48928

Which I got working and simulating fine. I am now trying to use what I learnt to run a simulation of my own logic in VHDL. I have set up my QSYS as per the attachment bfm.jpg I am using a bfm master to control the avalon mm slave components in the QSYS system. The aim of the simulation is to sample data from an ADC through a dcfifo connected as a streaming source, to a MM sram (using on chip memory for simulation) using a mSGDMA component. The adc_qsys and adc_sample are two user created components which I have simulated on their own and are functioning. My first question is:

1) Will connecting the streaming source of the ADC to the streaming sink of the mSGDMA and the mm master of the mSGDMA to the mm slave of the on chip ram simulate when I generate the qsys. Do I have to use another BFM for these paths?

Assuming that the QSYS system I have put together is valid. I have generated the QSYS. I created a VHDL simple test bench based on the example test bench in the tutorial, see attached qsys_bfm_system_tb.vhd as its too long to put in post.

So now I follow the tutorial:

I open modelsim ASE, I change directory to ..\qsys_bfm_test_system\simulation\mentor.

I run source msim_setup.tcl

com

vcom log_pkg and my testbench, which compile without any errors.

set TOP_LEVEL_NAME to qsys_bfm_test_system_tb

elab +nowarnTFMPC

now here is where I get confused. The elab returns a lot of warnings about not bound components. see attached modelsim_lib.jpg

note warnings

component instance "adc_qsys : qsys_bfm_test_system_adc_qsys" is not bound

component instance "adc_sample : qsys_bfm_test_system_adc_sample" is not bound

I also get a load of warnings about mm_interconnect and dispatcher.v and some other stuff. Now in the library window I can see adc_qsys and adc_sample have been compiled into libraries named adc_qsys and adc_sample. The tutorial did talk about this, so I included a library definition in my test bench to include these:

LIBRARY adc_qsys;
USE adc_qsys.adc_qsys.all;
LIBRARY adc_sample;
USE adc_sample.adc_sample.all;

I also tried:

LIBRARY adc_qsys;
USE work.adc_qsys.all;
LIBRARY adc_sample;
USE work.adc_sample.all;

But both resulted in same set of warnings in modelsim. When I look in the sim window of modelsim I can see the bfm_master the sram and the mSGDMA but there isnt the adc_qsys or adc_sample component. see attached mdelsim_sim.jpg When I run the simulation it doesnt work as there are no signals for adc_qsys or adc_sample.

2) can anyone help me with what is going wrong? I am hoping its something simple like I am not including the correct library? do I need to copy the user vhdl into the same simulation folder and compile it seperately?

Any help would be appreciated,

Thanks

James