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Altera_Forum
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11 years ago

QSYS BFM Simulation VHDL Help

Hi, I have followed the tutorial QSYS Avalon-MM Master BFM Tutorial for SystemVerilog and VHDL Testbenches: http://www.alteraforum.com/forum/showthread.php?t=48928 Which I got working...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Hi James,

Ok, I got the files, I'll take a look at them tonight.

Cheers,

Dave
SusanB's avatar
SusanB
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7 years ago

Was this ever solved? I am having the same problem with unbound components (for ADC IP), Quartus creating libraries with the same name as ADC IP, etc. Pulling my hair out on this one, came to the forum looking for answers, and finding that most of these are unresolved or unpublished solutions.