Qsys / Platform Designer - Using IP (i.e. FIFO) in Custom Component

I'm trying to build a custom component in Qsys / Platform Designer (Q18.0) and having issues instantiating a basic IP block, in a way that is intuitive, within the tools. As a very basic example, I'm trying to encapsulate a FIFO (32x32) and simply export the interfaces so that it could be instantiated in VHDL/Verilog. I'm oversimplifying at this point, but want to convince myself I can do it before making a project that's more complicated.

The issue that I'm running into is that the tools behave fine until the final Quartus build, in which case the tool does not see the files labeled [ip_name]_fifo_180_xxxxxxx.v, where [ip_name] is what I named the IP and xxxxxxx is the random character string affixed to the build of the IP. In this case file = a10_fifo_32x32_fifo_180_mxatppa.v

In the Component Editor tool (in "Files" tab), I can add the .QIP file associated with this IP (a10_fifo_32x32.qip) and the file pointers come across to Quartus build where Qsys project used. But, the individual files that QIP points to don't come with when Qsys project is built. Solutions would be to manually add these files in your new Quartus project or to manually add all of the files that .QIP file points to in the Component Editor. I opted for the latter option and got the project to build OK, but this is very clunky and would get very confusing with IP that's more complicated than a simple FIFO (only 4 files as source).

Am I missing something or is there an easier method for doing this? I see there is some documentation on using COMPOSITION_CALLBACK to create a system that's a lot more complicated than seems required to do something as simple as drag files pointed to by .QIP file when generating the project.

This is basically re-hashing a previous question that went unanswered a handful of years ago (see link below), but hoping to refresh the question and see if we can get an answer.

Thanks in advance!