Qsys / Platform Designer - Using IP (i.e. FIFO) in Custom Component

Thanks for the quick reply! I could absolutely do something like that, but potentially will have a bunch of channels / FIFOs internal to the design to connect that will get pretty ugly (fast) if all required interconnection via the Qsys tool. This exercise is mainly get the recipe for pulling in a pre-generated IP block. Just using a single FIFO here, but could be a plurality of FIFOs, PLLs, DPRAMs, etc. that I'd want to pull into a custom component.

It seems like a pretty likely use-case, unless everyone that's generating custom IP cores in Qsys is just designing with HDL? Or old Megawizard-era logic cores with source that's VHDL/Verilog at top level (instead of .QSYS / .QIP).

Thanks,

Jeff