Honored ContributorHi,
I'm using QuartusII 13.0sp1. In my Qsys design I'm using the Nios II/f version and the JTAGdebug module is set to Level 1. After compiling the QuartusII project, I can see from the Project Navigator that the jtag_debug_module is using 10,286 Logic Cells (out of 55,856 total), and that is just tooo much. How can I reduce this number?
Honored ContributorThat looks like a fifo made out of logic cells.
Are there any free internal memory blocks? Try minimising the sizes of the instruction and data caches to free some up.Honored ContributorFrom the Project Navigator window I can see 159 M9Ks being used in the design (I'm using the CycloneIII EP3C55 FPGA with 260 M9Ks). Total number of memory bits used is 805,183/2,396,160 (34 %). That would indicate sufficient internal memory for the fifo to be implemented in internal memory, right?
The Instruction cache is set to 4 Kbytes and the Data cache is using 2 Kbytes, so the caches are not using more than 5 - 6 M9K. Is there any settingn that will tell the synthesis tool to implement the fifo in internal memory blocks?Honored ContributorI have now been able to dramatically reduced the resource usage of the logic cells.
In the QSYS design I had a clock crossing bridge between the NiosII running at 100MHz and the DDR2 SDRAM controller running at 75MHz. I removed the clock crossing bridge and connected the NiosII instruction and data master directly to the slave port of the DDR2 SDRAM controller. Could it be the large address range of the masters connected through the clock crossing bridge that is causing the synthesis tool to implement such large fifo's using logic cells?
