QSYS - NIOSII - JTAG_DEBUG_MODULE using a lot of logic cells

From the Project Navigator window I can see 159 M9Ks being used in the design (I'm using the CycloneIII EP3C55 FPGA with 260 M9Ks). Total number of memory bits used is 805,183/2,396,160 (34 %). That would indicate sufficient internal memory for the fifo to be implemented in internal memory, right?

The Instruction cache is set to 4 Kbytes and the Data cache is using 2 Kbytes, so the caches are not using more than 5 - 6 M9K.

Is there any settingn that will tell the synthesis tool to implement the fifo in internal memory blocks?