Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

QSYS - NIOSII - JTAG_DEBUG_MODULE using a lot of logic cells

Hi, I'm using QuartusII 13.0sp1. In my Qsys design I'm using the Nios II/f version and the JTAGdebug module is set to Level 1. After compiling the QuartusII project, I can see from the P...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

That looks like a fifo made out of logic cells.

Are there any free internal memory blocks?

Try minimising the sizes of the instruction and data caches to free some up.