QSYS - NIOSII - JTAG_DEBUG_MODULE using a lot of logic cells

I have now been able to dramatically reduced the resource usage of the logic cells.

In the QSYS design I had a clock crossing bridge between the NiosII running at 100MHz and the DDR2 SDRAM controller running at 75MHz.

I removed the clock crossing bridge and connected the NiosII instruction and data master directly to the slave port of the DDR2 SDRAM controller.

Could it be the large address range of the masters connected through the clock crossing bridge that is causing the synthesis tool to implement such large fifo's using logic cells?