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Altera_Forum's avatar
Altera_Forum
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11 years ago

Q14 Web edition replace top level out port with buffer

Hi

I've done a top layer entity with (of course) some out port. I also made a testbench in order to verify the design. The problem is that Quartus sometimes generate a post-fitting simulation same as the entity I declare but with a buffer port instead the out port. In this way I can't run the post-fitting simulation. I have to recreate the project, that is quite annoying. Any work around?

Thanks in advice

Filippo

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I assume you're referring to VHDL's buffer port mode? do you read the output in the file internally?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Yes, most of them, but using an internal signal and not in the top level.. something like

    entity x is

    port(

    ...

    ...

    ...

    output : out std_logic

    );

    architecture b of x is

    signal output_signal : std_logic;

    begin

    -- some logic that read also output_signal

    output <= output_signal;

    end b;
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I can only guess that the synth optimisations have removed your internal signal, and so then reading the output port is required - meaning it needs to be a buffer rather than output (in 1993 at least - this restriction is removed in 2008).

    try using a syn_keep attribute on the output_signal
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Any other work around? i prefer to not affect the vhdl code.

    thanks