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Altera_Forum
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11 years ago

Q14 Web edition replace top level out port with buffer

Hi I've done a top layer entity with (of course) some out port. I also made a testbench in order to verify the design. The problem is that Quartus sometimes generate a post-fitting simulation s...
Altera_Forum's avatar
Altera_Forum
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11 years ago

I assume you're referring to VHDL's buffer port mode? do you read the output in the file internally?