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Altera_Forum's avatar
Altera_Forum
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11 years ago

Q14 Web edition replace top level out port with buffer

Hi I've done a top layer entity with (of course) some out port. I also made a testbench in order to verify the design. The problem is that Quartus sometimes generate a post-fitting simulation s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Yes, most of them, but using an internal signal and not in the top level.. something like

entity x is

port(

...

...

...

output : out std_logic

);

architecture b of x is

signal output_signal : std_logic;

begin

-- some logic that read also output_signal

output <= output_signal;

end b;