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Altera_Forum
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17 years ago

Pull-ups/Pull-Down/Slew-Rate I/O pins definitions

Hello,

Scoured the Quartus/Cyclone-III docs for methods of defining Pull-ups/Pull-Down/Slew-Rate for I/O pins, but to no avail.

1. I understand that most of the device's I/O have internal Weak Pull-Ups. But how to change these definitions to Strong Pull-ups, or Pull Downs ?

2. And, how about chaging the values of default Slew Rates ?

3. Also relevant to these questions, I found in the HELP a mention to a "User Mode" - what is this ? And how is it relevant to issues (1) & (2) above ?

TIA,

Roli

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Generally, a brief explanation of available options can be found in Cyclone III device handbook under i/o element features. The options can be set for individual pins or groups of pins in quartus assignment editor or more conveniently in Pin Planner. In the Pin Planner you can enable additional columns to control the said I/O features. As said in the handbook, not all options can be used simultaneously, some are mutial exclusive.

    A programmable weak pull-up exist at all regular I/O pins, but not for dedicated clock inputs or configurations pins. The weak pull-ups are allways enabled, before the user defined FPGA configuration is in effect but disabled when the configuration gets active by default. The configured operation is also designated user mode.

    The default behaviour can be changed to enable the weak pull-up also in user mode, e. g. for an input that reads a configuration switch or to set a bidirectional bus to a defined state. No different resistor value or pull-down is available, the term programmable means on/off only. In addition, parallel termination resistors can be activated for differential inputs with some FPGA, but not with Cyclone III.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks you very much for the clear and precise info !

    A few questions remain:

    --- Quote Start ---

    The weak pull-ups are allways enabled, before the user defined FPGA configuration is in effect but disabled when the configuration gets active by default.

    The default behaviour can be changed to enable the weak pull-up also in user mode, e. g. for an input that reads a configuration switch or to set a bidirectional bus to a defined state....

    --- Quote End ---

    1. Does this mean that, when in default behavior, there are always 'weak pull-ups' BEFORE & AFTER Configuration ('user mode'), but not during ?

    2. And, how can this default behavior be changed ?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    There is no after user mode state normally, unless you reset the configuration by asserting nconfig or reprogram the device through JTAG. The weak pull-ups are provided by Altera to assure defined behaviour and avoid excessive current consumption of input drivers caused by floating pins with mid-scale input voltage. They can't be changed.

    The only disadvantage of weak pull-ups is, that you need a 2k2 or below external pulldown for an output, that must be assured to stay at low level in unconfigured state. So, for a low power design, it may be meaninful to use an external inverter instead.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks.

    BTW - I have tried the "Custumize Column" option (in the Pin Planner) - and to my surprise there are options for adding:

    1. "Near Pull-up resistance" - I assume this gives an option for defining a real resistor value ? Any value ? What is the meaning of "Near" & "Far" ?

    2. "Near Pull-down resistance" - as opposed to what you have stated ! (or, that this is NOT available for the Cyclone-III ?)
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The said items are no available FPGA resources (I think with no family) but external termination elements to be considered in output load calculation and signal integrity checks.