Pull-ups/Pull-Down/Slew-Rate I/O pins definitions

Generally, a brief explanation of available options can be found in Cyclone III device handbook under i/o element features. The options can be set for individual pins or groups of pins in quartus assignment editor or more conveniently in Pin Planner. In the Pin Planner you can enable additional columns to control the said I/O features. As said in the handbook, not all options can be used simultaneously, some are mutial exclusive.

A programmable weak pull-up exist at all regular I/O pins, but not for dedicated clock inputs or configurations pins. The weak pull-ups are allways enabled, before the user defined FPGA configuration is in effect but disabled when the configuration gets active by default. The configured operation is also designated user mode.

The default behaviour can be changed to enable the weak pull-up also in user mode, e. g. for an input that reads a configuration switch or to set a bidirectional bus to a defined state. No different resistor value or pull-down is available, the term programmable means on/off only. In addition, parallel termination resistors can be activated for differential inputs with some FPGA, but not with Cyclone III.