Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorProcess Statement must contain only one Wait Statement : More WAIT
Hi,
I try to use a code but there are more WAIT. How can i change it ???? I change "wait until" to wait until Clk'event ????
StartTx <= '0';
DataToTx_M <= "0101010101010101";
DataToTx_S <= "1010101010101010";
--wait until Clk = '1';
wait until Clk'event and Clk='1';
reset <= '0';
--wait until Clk = '1';
wait until Clk'event and Clk='1';
StartTx <= '1';
wait until Clk = '1';
StartTx <= '0';
5 Replies
Altera_ForumThe rule is correct - you can only have 1 wait statement in a process if you want to compile the code for an fpga.
Your code looks like software, not hardware. I highly recommend you find a VHDL tutorial or VHDL textbook that has digital logic examples. VHDL is a hardware description language, not a programming language. Have you drawn your circuit on paper (or visio or something) before you tried to write the code? as a description language, you need to know what you are describing first.- Altera_Forum--- Quote Start --- The rule is correct - you can only have 1 wait statement in a process if you want to compile the code for an fpga. Your code looks like software, not hardware. I highly recommend you find a VHDL tutorial or VHDL textbook that has digital logic examples. VHDL is a hardware description language, not a programming language. Have you drawn your circuit on paper (or visio or something) before you tried to write the code? as a description language, you need to know what you are describing first. --- Quote End --- Thanks BUT it is a sample that find on web !!!!! How can i change this code ??? Best regards Jennifer
- Altera_Forum
THis code sample you have found is probably from a testbench, where many wait statements are allowed and often required.
- Altera_Forum--- Quote Start --- THis code sample you have found is probably from a testbench, where many wait statements are allowed and often required. --- Quote End --- Yes you are right, the name is "tb" I look for a SPI Master programme. Thanks Jennifer
- Altera_Forum
When writing code for an FPGA it's best to avoid using wait, it will make code more difficult to read, and too tempting to put several of them, making it impossible for the software to synthesize. It's better to stick with the recommended template for a clocked process:
Codes for test benches usually can't directly be adapted for synthesis, you have to rethink the design. I recommend to use a state machine that can generate a reset pulse if needed, then wait for some data to transmit and send it on the SPI bus. You'll also need a bit counter and a shift register.<optional_label>: process(reset, clk) is -- Declaration(s) begin if(reset = '1') then -- Asynchronous Sequential Statement(s) elsif(rising_edge(clk)) then -- Synchronous Sequential Statement(s) end if; end process;
