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Altera_Forum
Honored Contributor
Honored ContributorProcess Statement must contain only one Wait Statement : More WAIT
Hi, I try to use a code but there are more WAIT. How can i change it ???? I change "wait until" to wait until Clk'event ????
StartTx <= '0';
DataToTx_M <= "0101010101010101";
DataToTx_S...
Altera_ForumHonored Contributor
Honored ContributorThe rule is correct - you can only have 1 wait statement in a process if you want to compile the code for an fpga.
Your code looks like software, not hardware. I highly recommend you find a VHDL tutorial or VHDL textbook that has digital logic examples. VHDL is a hardware description language, not a programming language. Have you drawn your circuit on paper (or visio or something) before you tried to write the code? as a description language, you need to know what you are describing first.
