Process Statement must contain only one Wait Statement : More WAIT

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The rule is correct - you can only have 1 wait statement in a process if you want to compile the code for an fpga.

Your code looks like software, not hardware. I highly recommend you find a VHDL tutorial or VHDL textbook that has digital logic examples.

VHDL is a hardware description language, not a programming language. Have you drawn your circuit on paper (or visio or something) before you tried to write the code? as a description language, you need to know what you are describing first.

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Thanks BUT it is a sample that find on web !!!!! How can i change this code ???

Best regards

Jennifer