Process Statement must contain only one Wait Statement : More WAIT

When writing code for an FPGA it's best to avoid using wait, it will make code more difficult to read, and too tempting to put several of them, making it impossible for the software to synthesize. It's better to stick with the recommended template for a clocked process:

<optional_label>:
        process(reset, clk) is 
                -- Declaration(s) 
        begin 
                if(reset = '1') then
                        -- Asynchronous Sequential Statement(s) 
                elsif(rising_edge(clk)) then
                        -- Synchronous Sequential Statement(s)
                end if;
        end process; 

Codes for test benches usually can't directly be adapted for synthesis, you have to rethink the design. I recommend to use a state machine that can generate a reset pulse if needed, then wait for some data to transmit and send it on the SPI bus. You'll also need a bit counter and a shift register.