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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with generate statement in Verilog

I want to instantiate different modules controlled by an input "Mode".

Here are my code in Verilog:

generate case (Mode) 1: begin : case1

(instantiate module 1)

end

0: begin : case0

(instantiate module 0)

end

endcase

[/INDENT]endgenerate

Quartus II 9.1 gives an error

Error (10734): Verilog HDL error at Test.v(215): Mode is not a constant.

Does generate statement only use constant as conditions?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Does generate statement only use constant as conditions?

    --- Quote End ---

    Obviously. Generate means building a particular design part once or repeatedly, or omit it. This must be determined at compile time. What do you want to achieve?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I try to make it work with different plug-in devices which require different timing signals. It seems the only way I can do is to instantiate both modules and use muxers.