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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with generate statement in Verilog

I want to instantiate different modules controlled by an input "Mode". Here are my code in Verilog: generate case (Mode) 1: begin : case1 (instantiate module 1) ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Does generate statement only use constant as conditions?

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Obviously. Generate means building a particular design part once or repeatedly, or omit it. This must be determined at compile time. What do you want to achieve?