Honored ContributorHi all,
Ok, I found out that SDRAM keeps writing forever and never stop, when I call IOWR_32DIRECT(...) in SignalTap. When I look at Dev Board Cyclone II and it does show Write and Burst Terminate in SignalTap. My board is Cyclone III with MT48LC4M32B2-7. Maybe clock phase shift or something else. Thanks for read my post and help. Sean
Honored Contributornot much info, but yes, you will need to do a clock phase shift between the clock that is driving your SDRAM chip and the clock that is driving your SDRAM controller block. There is some latency though the SDRAM controller. This is not necessarily your problem though. You should be using two seperate clocks. You can have several clocks out of one PLL. They need to be the same clock rate, just delay one of them. You can do it by trial and error and find out what the upper and lower bounds are for proper operation then split the difference. If you give more info like what clock rate and how your SOPC architecture is setup it might help.
Honored ContributorThanks. I have sys_clk is 100mhz and sdram_clk is 133mhz...my phase shift is -3.5ns.
pll.c0 goes to sys_clk Nios 1/1 and 0deg pll.c1 goes to output sdram_clk 4/3 = 133mhz and -3.5ns pll.c2 goes to output sys_clk 1/1 and 0deg Thanks. SeanHonored ContributorYou should also constrain your memory interface. It might not be even necessary to phase shift the clock is you provide proper constraints since the fitter might be able to compensate for the offchip timing.
Honored ContributorOk. Where can I get that information about constrain memory interface? Is there documents online to show me how? I've been looked into TimeQuest, but I don't know where to start... SDC, Create Clock, Set Input Delay... Set Output Delay...
How about I post my design, maybe you could take a look at it? Thanks, SeanHonored Contributorthere is some info on constraining SOPC systems if you search on this blog. I can tell you that the clock phase shift is all that is necessary though.
Have you done a timing analysis? Are you passing timing with the SDRAM controller running at 133? I could barley get mine to run at 100Mhz on a CIII spd grade 8. Have you tried running all are you using a custom SDRAM controller or one that is preconfigured in SOPC builder?Honored ContributorThanks.
I did try custom and without custom for SDRAM controller in SOPC. In pll, I select Any for speed. I also tried to set sys_clk to 50mhz and sdram_clk to 50mhz and still no luck. I need to get this SDRAM working... bc my design already works on dev board with SGDMA -> FIFO -> FIFO -> SGDMA The weird thing is that when I write to sdram. It never stops. My look like this WRITE –----- -à Gone with the wind But actual should looks like this WRITE – NOP – PRECHARGE – NOP – ACTIVE Best regards, SeanHonored Contributorok, i just looked in sopc, so the memory you are using is already setup, so your controller should be working.
I think you just need to get your clocking right. Let me understand your system. You have a Nios II and you have the memory in SOPC builder. And you have a PLL in SOPC or outside of SOPC? You basically need to have 1 clock that is driving the SDRAM controller from your PLL and then you need to have another clock that is exported out of your SOPC or top level file off the FPGA to the clock pin of the SDRAM. The clock that is driving the SDRAM should have a delay of around -3ns. You need to be doing a timing analysis and putting timing constraints in your design so that at a very minimum, quartus knows what clocks everything is running off of. In your .SDC file you should have something like this: create_clock -period 20.000 -name ext_clk [get_ports {clk50}] derive_pll_clocks derive_clock_uncertainty where clk50 is the name of your input clock pin that is driving the FPGA. and 20 is the period of that clock. In my case I have a 50Mhz osc hooked to my PLL input. If you have all of this and still can't get it to work it maybe a software problem or pin mapping problem.Honored Contributoralso, in software, you can do something like this to test your memory.
alt_u32* sdram = (alt_u32*) SDRAM_BASE; where SDRAM_BASE is the base address of your SDRAM controller. You can find that in your system.h file. for(i=0;i<10000;i++) { sdram[i] = i; } then in the debugger, you can load sdram variable as an array and verify the result of your for loop.Honored ContributorThanks. I will try that and I also include the pictures of my design.
Best regards, SeanHonored ContributorHi spaugh,
I'm using sys_clk=50mhz, sdram=50mhz, and phase shift=0. When I do Generate SDC File From QSF, I do see the result like this create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}] create_clock -name {sys_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_clk}] create_clock -name {sdram_clk} -period 7.518 -waveform { 0.000 3.759 } [get_ports {sdram_clk}] Unconstrained Paths Summary Illegal Clocks 0 0 Unconstrained Clocks 0 0 Unconstrained Input Ports 35 35 Unconstrained Input Port Paths 195 195 Unconstrained Output Ports 56 56 Unconstrained Output Port Paths 88, 88 Thanks for your help. Sean
