Problem SDRAM....Burst Terminate!!!

ok, i just looked in sopc, so the memory you are using is already setup, so your controller should be working.

I think you just need to get your clocking right.

Let me understand your system.

You have a Nios II and you have the memory in SOPC builder.

And you have a PLL in SOPC or outside of SOPC?

You basically need to have 1 clock that is driving the SDRAM controller from your PLL and then you need to have another clock that is exported out of your SOPC or top level file off the FPGA to the clock pin of the SDRAM.

The clock that is driving the SDRAM should have a delay of around -3ns.

You need to be doing a timing analysis and putting timing constraints in your design so that at a very minimum, quartus knows what clocks everything is running off of.

In your .SDC file you should have something like this:

create_clock -period 20.000 -name ext_clk [get_ports {clk50}]

derive_pll_clocks

derive_clock_uncertainty

where clk50 is the name of your input clock pin that is driving the FPGA. and 20 is the period of that clock. In my case I have a 50Mhz osc hooked to my PLL input.

If you have all of this and still can't get it to work it maybe a software problem or pin mapping problem.