Problem SDRAM....Burst Terminate!!!

not much info, but yes, you will need to do a clock phase shift between the clock that is driving your SDRAM chip and the clock that is driving your SDRAM controller block. There is some latency though the SDRAM controller. This is not necessarily your problem though. You should be using two seperate clocks. You can have several clocks out of one PLL. They need to be the same clock rate, just delay one of them. You can do it by trial and error and find out what the upper and lower bounds are for proper operation then split the difference. If you give more info like what clock rate and how your SOPC architecture is setup it might help.