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Altera_Forum
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15 years ago

Problem SDRAM....Burst Terminate!!!

Hi all, Ok, I found out that SDRAM keeps writing forever and never stop, when I call IOWR_32DIRECT(...) in SignalTap. When I look at Dev Board Cyclone II and it does show Write and Bur...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks. I have sys_clk is 100mhz and sdram_clk is 133mhz...my phase shift is -3.5ns.

pll.c0 goes to sys_clk Nios 1/1 and 0deg

pll.c1 goes to output sdram_clk 4/3 = 133mhz and -3.5ns

pll.c2 goes to output sys_clk 1/1 and 0deg

Thanks.

Sean