Problem SDRAM....Burst Terminate!!!

Hi spaugh,

I'm using sys_clk=50mhz, sdram=50mhz, and phase shift=0. When I do Generate SDC File From QSF, I do see the result like this

create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]

create_clock -name {sys_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_clk}]

create_clock -name {sdram_clk} -period 7.518 -waveform { 0.000 3.759 } [get_ports {sdram_clk}]

Unconstrained Paths Summary

Illegal Clocks 0 0

Unconstrained Clocks 0 0

Unconstrained Input Ports 35 35

Unconstrained Input Port Paths 195 195

Unconstrained Output Ports 56 56

Unconstrained Output Port Paths 88, 88

Thanks for your help.

Sean