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Altera_Forum
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16 years ago

problem of setting max_fanout

Below is the critical path of my design. As you can see, several cells has big fanout, so the IC delay is big. I want to constrain max_fanout to 10 to reduce IC delay. But how to set it? I tried to set like"set_instance_assignment -name MAX_FANOUT -to ctx". However it doesn't work. How should I write this assignment?

Thanks!

+-----------------------------------------------------------------------------------------------------------------------+

; Data Arrival Path ;

+--------+-------+----+------+--------+----------------------+----------------------------------------------------------+

; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;

+--------+-------+----+------+--------+----------------------+----------------------------------------------------------+

; 0.000 ; 0.000 ; ; ; ; ; launch edge time ;

; 2.604 ; 2.604 ; R ; ; ; ; clock network delay ;

; 2.663 ; 0.059 ; ; uTco ; 1 ; FF_X54_Y44_N13 ; dec_t1_regfile:udec_t1_regfile|reg_sgnf[38] ;

; 2.663 ; 0.000 ; FF ; CELL ; 15 ; FF_X54_Y44_N13 ; udec_t1_regfile|reg_sgnf[38]|q ;

; 2.880 ; 0.217 ; FF ; IC ; 1 ; LABCELL_X54_Y44_N8 ; udec_t1_needcoding|Selector9~3|dataa ;

; 3.193 ; 0.313 ; FR ; CELL ; 2 ; LABCELL_X54_Y44_N8 ; udec_t1_needcoding|Selector9~3|combout ;

; 3.454 ; 0.261 ; RR ; IC ; 1 ; LABCELL_X56_Y44_N36 ; udec_t1_needcoding|Selector9~2|datae ;

; 3.604 ; 0.150 ; RF ; CELL ; 6 ; LABCELL_X56_Y44_N36 ; udec_t1_needcoding|Selector9~2|combout ;

; 4.079 ; 0.475 ; FF ; IC ; 1 ; MLABCELL_X57_Y43_N38 ; udec_t1_needcoding|o_exist_codingbit~15_RESYN42|dataa ;

; 4.397 ; 0.318 ; FR ; CELL ; 2 ; MLABCELL_X57_Y43_N38 ; udec_t1_needcoding|o_exist_codingbit~15_RESYN42|combout ;

; 4.568 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X57_Y43_N14 ; udec_t1_needcoding|o_exist_codingbit~15DUPLICATE|datae ;

; 4.715 ; 0.147 ; RR ; CELL ; 6 ; MLABCELL_X57_Y43_N14 ; udec_t1_needcoding|o_exist_codingbit~15DUPLICATE|combout ;

; 4.848 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X57_Y43_N18 ; udec_t1_needcoding|o_codingbit_position[0]~99|datac ;

; 5.040 ; 0.192 ; RR ; CELL ; 1 ; MLABCELL_X57_Y43_N18 ; udec_t1_needcoding|o_codingbit_position[0]~99|combout ;

; 5.160 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X57_Y43_N8 ; udec_t1_needcoding|o_codingbit_position[0]~100|dataa ;

; 5.482 ; 0.322 ; RR ; CELL ; 28 ; MLABCELL_X57_Y43_N8 ; udec_t1_needcoding|o_codingbit_position[0]~100|combout ;

; 5.969 ; 0.487 ; RR ; IC ; 1 ; MLABCELL_X57_Y45_N12 ; udec_t1_ctxgen|Mux3~21|datad ;

; 6.217 ; 0.248 ; RR ; CELL ; 12 ; MLABCELL_X57_Y45_N12 ; udec_t1_ctxgen|Mux3~21|combout ;

; 6.363 ; 0.146 ; RR ; IC ; 1 ; MLABCELL_X57_Y45_N36 ; udec_t1_ctxgen|Mux3~11|datac ;

; 6.553 ; 0.190 ; RR ; CELL ; 8 ; MLABCELL_X57_Y45_N36 ; udec_t1_ctxgen|Mux3~11|combout ;

; 6.872 ; 0.319 ; RR ; IC ; 1 ; LABCELL_X60_Y45_N38 ; udec_t1_ctxgen|sigma_hvd|datad ;

; 7.073 ; 0.201 ; RF ; CELL ; 1 ; LABCELL_X60_Y45_N38 ; udec_t1_ctxgen|sigma_hvd|combout ;

; 7.161 ; 0.088 ; FF ; IC ; 1 ; LABCELL_X60_Y45_N0 ; udec_t1_ctxgen|Selector10~2|dataf ;

; 7.220 ; 0.059 ; FR ; CELL ; 1 ; LABCELL_X60_Y45_N0 ; udec_t1_ctxgen|Selector10~2|combout ;

; 7.339 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X60_Y45_N20 ; udec_t1_ctxgen|Selector10~5|dataa ;

; 7.663 ; 0.324 ; RR ; CELL ; 1 ; LABCELL_X60_Y45_N20 ; udec_t1_ctxgen|Selector10~5|combout ;

; 8.582 ; 0.919 ; RR ; IC ; 1 ; IOOBUF_X91_Y45_N113 ; ctx[0]~output|i ;

; 10.836 ; 2.254 ; RR ; CELL ; 1 ; IOOBUF_X91_Y45_N113 ; ctx[0]~output|o ;

; 10.836 ; 0.000 ; RR ; CELL ; 0 ; PIN_N1 ; ctx[0] ;

+--------+-------+----+------+--------+----------------------+----------------------------------------------------------+

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I've only used that assignment for registers, and imagine that's all its meant for. Even if you were able to apply it to a combinatorial node, those nodes commonly change names on different synthesis passes, and the assignment would probably break.

    Also, the fanouts in here are actually quite small. Note that, unlike an ASIC, the delays of large fanout nets don't increase much because of loading, but are more distance based. So, for example, the one that has a fanout of 28 and IC delay of 0.487ns, has that longer delay because it's hopping to a different LAB. If you were to replicate that node, the destination would still be in another LAB, and you'd still have a similar delay(or if the replicant were moved into that LAB, then you'd just have move that hop delay back one). I would look at Tools -> Advisors -> Timing Optimization and see if there is anything there that can help.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thank you very much for this explanation. I am new to FPGA design. thanks a lot!

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi,

    You can try: 

    "set_instance_assignment -name MAX_FANOUT -to dec_t1_regfile:udec_t1_regfile|*"

    That should cover entire udec_t1_regfile instance.

    Synthesis report <project>.map.rpt will produce "Registers Duplicated to Honor Maximum Fanout Requirements" section.

    It lists all the registers, required fanout and number of duplicated registers created for those registers.

    You can verify which entities the constraint was applied to, and how those entities were duplicated.

    Thanks,

    Evgeni