Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI've only used that assignment for registers, and imagine that's all its meant for. Even if you were able to apply it to a combinatorial node, those nodes commonly change names on different synthesis passes, and the assignment would probably break.
Also, the fanouts in here are actually quite small. Note that, unlike an ASIC, the delays of large fanout nets don't increase much because of loading, but are more distance based. So, for example, the one that has a fanout of 28 and IC delay of 0.487ns, has that longer delay because it's hopping to a different LAB. If you were to replicate that node, the destination would still be in another LAB, and you'd still have a similar delay(or if the replicant were moved into that LAB, then you'd just have move that hop delay back one). I would look at Tools -> Advisors -> Timing Optimization and see if there is anything there that can help.