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Altera_Forum's avatar
Altera_Forum
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16 years ago

problem of setting max_fanout

Below is the critical path of my design. As you can see, several cells has big fanout, so the IC delay is big. I want to constrain max_fanout to 10 to reduce IC delay. But how to set it? I tried to s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

You can try: 

"set_instance_assignment -name MAX_FANOUT -to dec_t1_regfile:udec_t1_regfile|*"

That should cover entire udec_t1_regfile instance.

Synthesis report <project>.map.rpt will produce "Registers Duplicated to Honor Maximum Fanout Requirements" section.

It lists all the registers, required fanout and number of duplicated registers created for those registers.

You can verify which entities the constraint was applied to, and how those entities were duplicated.

Thanks,

Evgeni