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Altera_Forum's avatar
Altera_Forum
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16 years ago

problem of setting max_fanout

Below is the critical path of my design. As you can see, several cells has big fanout, so the IC delay is big. I want to constrain max_fanout to 10 to reduce IC delay. But how to set it? I tried to s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thank you very much for this explanation. I am new to FPGA design. thanks a lot!