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Honored ContributorPost Synthesis simulation fails, problem with RTL?
Hello all, I have a relatively simple state machine that works just fine for functional pre-synthesis simulation in Modelsim.
However, after running Quartus synthesis and fitter and extracting the post synthesis netlist (.vdo) the post synthesis simulation fails. I have narrowed down the problem to a particular counter that counts correctly pre-syn but does not count at all post syn. Here are the code segments. Does anyone see what I am doing wrong that causes Quartus to mis-interpret the "increment reg"? I am using Quartus 13. Thanks in advance for any suggestions. --here is the increment register process-- inc_reg : process(clock, inc_reset, increment, increment_input)is begin if inc_reset = '0' then increment_input <= "0000"; elsif rising_edge(clock) then if increment = '1' then increment_input <= increment_input + 1; else increment_input <= increment_input; end if; end if; end process inc_reg; --here are the states that should cause it to increment------------------------------ when key_data_input => inc_reset <= '1'; oe1 <= '1';-- send to chip OE <= '0'; RD <= '1'; WR <= '0'; CS <= '0'; A0 <= '0'; DIR <= '0';-- FPGA to Chip timer_start <= '1';-- counter timer2_start <= '0'; data_start <= '0'; --output_enable <= '0'; if counter <= "001010" then increment <= '0'; else increment <= '1'; end if; if increment_input = "0000" then data_to_bus (7 downto 1) <= key (55 downto 49); data_to_bus (0) <= parity0; elsif increment_input = "0001" then data_to_bus (7 downto 1) <= key (48 downto 42); data_to_bus (0) <= parity1; elsif increment_input = "0010" then data_to_bus (7 downto 1) <= key (41 downto 35); data_to_bus (0) <= parity2; elsif increment_input = "0011" then data_to_bus (7 downto 1) <= key (34 downto 28); data_to_bus (0) <= parity3; elsif increment_input = "0100" then data_to_bus (7 downto 1) <= key (27 downto 21); data_to_bus (0) <= parity4; elsif increment_input = "0101" then data_to_bus (7 downto 1) <= key (20 downto 14); data_to_bus (0) <= parity5; elsif increment_input = "0110" then data_to_bus (7 downto 1) <= key (13 downto 7); data_to_bus (0) <= parity6; elsif increment_input = "0111" then data_to_bus (7 downto 1) <= key (6 downto 0); data_to_bus (0) <= parity7; else data_to_bus <= "00000000"; end if; when key_data_input_pause => increment <= '0'; inc_reset <= '1'; oe1 <= '0';-- read chip OE <= '0'; RD <= '1'; WR <= '1'; CS <= '0'; A0 <= '0'; DIR <= '1';-- Chip to FPGA timer_start <= '0'; timer2_start <= '1';-- counter set mode data_to_bus <= "11111111"; data_start <= '0'; when key_SRQ => increment <= '0'; inc_reset <= '1'; oe1 <= '0';-- read chip OE <= '0'; RD <= '1'; WR <= '1'; CS <= '0'; A0 <= '1'; DIR <= '1';-- Chip to FPGA timer_start <= '0'; timer2_start <= '0'; data_to_bus <= "11111111"; data_start <= '0'; -- here are the state transitions---------------------------------------------------- when key_data_input => if counter <= "001010" then next_state <= key_data_input; else next_state <= key_data_input_pause; end if; when key_data_input_pause => if counter_set_mode < "100000" then next_state <= key_data_input_pause; elsif increment_input > "0111" then next_state <= check_KPE; else next_state <= key_SRQ; end if; when key_SRQ => if SRQ = '1' then next_state <= key_data_input; else next_state <= key_data_input_pause; end if;
