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Altera_Forum
Honored Contributor
Honored ContributorPost Synthesis simulation fails, problem with RTL?
Hello all, I have a relatively simple state machine that works just fine for functional pre-synthesis simulation in Modelsim. However, after running Quartus synthesis and fitter and extracting the...
Altera_ForumHonored Contributor
Honored ContributorYou didnt post the whole code, so I have to assume you're using a 2 process state machine style?
increment appears to not be set in all states, so a latch will be created. Latches can have timing problems in hardware - so it is recommended that you avoid them.
