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Altera_Forum
Honored Contributor
Honored ContributorPost Synthesis simulation fails, problem with RTL?
Hello all, I have a relatively simple state machine that works just fine for functional pre-synthesis simulation in Modelsim. However, after running Quartus synthesis and fitter and extracting the...
Altera_ForumHonored Contributor
Honored ContributorHi Tricky, yes I am using the traditional two process state machine. I did not post the whole code for brevity.
these are the only states that activate the increment process with the "increment" and "inc_reset" signals. increment is actively controlled in all states, unless you are seeing something above that I am not. No latches are inferred during the synthesis process.
