positive edge-triggered D-type flip-flops

If you use Quartus II, just do the following:

- create a new file

- in the empty editor right mouse button, select insert template

- choose VHDL, then Logic, the Registers, the whatever Register posivite edge you like

- hit insert

- done

you get:

-- In Altera devices, register signals have a set priority.

-- The HDL design should reflect this priority.

process(<reset>, <aload>, <adata>, <clock_signal>)

begin

-- The asynchronous reset signal has the highest priority

if (<reset> = '0') then

<register_variable> <= '0';

-- Asynchronous load has next-highest priority

elsif (<aload> = '1') then

<register_variable> <= <adata>;

else

-- At a clock edge, if asynchronous signals have not taken priority,

-- respond to the appropriate synchronous signal.

-- Check for synchronous reset, then synchronous load.

-- If none of these takes precedence, update the register output

-- to be the register input.

if (rising_edge(<clock_signal>)) then

if (<clock_enable> = '1') then

if (<synch_reset> = '0') then

<register_variable> <= '0';

elsif (<synch_load> = '1') then

<register_variable> <= <synch_data>;

else

<register_variable> <= <data>;

end if;

end if;

end if;

end if;

end process;

whereas all the <variablename> can be ports, a very simple DFF that can be used as a sheet symbol:

-- Quartus II VHDL Template

-- Basic DFF

library ieee;

use ieee.std_logic_1164.all;

entity DFF is

port

(

clk : in std_logic;

clk_ena : in std_logic;

data : in std_logic;

reset : in std_logic;

q : out std_logic

);

end entity;

architecture rtl of DFF is

signal internal_state : std_logic;

begin

process(data, clk, clk_ena, reset)

begin

if(reset = '0') then

if rising_edge(clk) then

if(clk_ena = '1') then

internal_state <= data; --latch input

end if;

q <= internal_state;

end if;

else

internal_state <= '0';

end if;

end process;

end rtl;

note: I didn't compile it, but it should work. It lacks async. load, but I never use that, since apart from resets, async designs are a pain in the

*bleep*.

VHDL:

d_proc : process(clk, reset)
begin
  if reset = '1' then --async reset
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

AHDL:

reg : dff;
reg.reset = reset;
reg.clk = clk;
reg.d   = input;
reg.q   = output;