positive edge-triggered D-type flip-flops

VHDL:

d_proc : process(clk, reset)
begin
  if reset = '1' then --async reset
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

reg : dff;
reg.reset = reset;
reg.clk = clk;
reg.d   = input;
reg.q   = output;