Honored ContributorHi all,
I want to implement a PLL that will lock onto & track an incoming signal of about 30KHz and output a multiple of that locked frequency. I tried using Quartus's PLL megacore function but it wont accept a 30KHz input signal, saying that its too low. Is there something I might be doing wrong or do I have to design my own PLL using the an XOR,NCO & the FIR filter megacores(if thats even possible)???
Honored ContributorSo are you saying that with an XOR as the phase comparator, there will be a phase shift?
Which ones yield a zero phase shift?Honored ContributorI think, available PLL literature can tell better. A FF based phase comparator (see e.g. a CD4046 PLL datasheet for reference) generally achieves 0 phase shift and a larger lock range because it avoids locking on harmonics. You can assume, that FPGA internal PLLs are using a phase comparator of this type.
Please consider, that the phase comparator output of a classical PLL is an analog signal, at least after averaging it in the loop filter. An "all digital" PLL in contrast acquires the phase difference as numerical value and uses digital signal processing to calculate a VCO control value, e.g. a NCO phase increment.Honored ContributorSo then with an all digital pll, there would be no need for a loop filter(it would be replaced with a subsystem that takes the phase comparator output and calculates the appropriate NCO input in order to achieve lock)?
Honored ContributorIt's a kind of loop filter as well.
Honored ContributorHi guys! Happy New Year!
I got a working PLL and managed to modify it to do what I want it to do..well almost. Does anyone know how to cause a clock to have a 50% duty cycle?? The NCO's output clock (I hardlimit the output sine wave to get a clock) seems to have glitches with its duty cycle : every so often the duty cycle is less/more than 50%. This eventually accumulates and my clock drifts.Honored Contributor