PLL megacore probs.build my own??

I think, available PLL literature can tell better. A FF based phase comparator (see e.g. a CD4046 PLL datasheet for reference) generally achieves 0 phase shift and a larger lock range because it avoids locking on harmonics. You can assume, that FPGA internal PLLs are using a phase comparator of this type.

Please consider, that the phase comparator output of a classical PLL is an analog signal, at least after averaging it in the loop filter. An "all digital" PLL in contrast acquires the phase difference as numerical value and uses digital signal processing to calculate a VCO control value, e.g. a NCO phase increment.