PLL Intel FPGA IP zero delay buffer mode pass at elaboration but failed at compilation

You should have if/else in your reset block, not two separate if statements.

You should have a final default clause in your case statement.

I think you're also missing the fbclk input pin that gets enabled in zero-delay buffer mode that's required for the feedback loop for the PLL.

Refer, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf?wapkw=altera%20pll#page=9

Zero-Delay Bu er mode—the PLL feedback path is confined to the dedicated PLL external output pin. The clock port driven o -chip is phase aligned with the clock input for a minimal delay between the clock input and the external clock output.

Also, Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration (intel.com)

You don't have to generate a feedback clock in your code. Need to simply assign zdbfbclk as an inout port in the top module.

Here is the changed code:

module PLL_DRP(

input REFCLK,

input RESET,

output outclk_0,

output outclk_1,

output reg outclk_fb,

inout zdbfbclk,

output reg sel,

output locked

);

always @ (posedge REFCLK)

begin

if(RESET) sel <= 1'b0;

else

begin

if(sel==1'b0) sel <= 1'b1;

if(sel==1'b1) sel <= 1'b0;

end

end

always @ (*)

begin

case (sel)

8'h00 : outclk_fb <= outclk_0;

8'h01 : outclk_fb <= outclk_1;

endcase

end

assign oe = 1'b1;

//assign zdbfbclk = oe ? outclk_fb : 1'bZ;

PLL_DRP_IP PLL_DRP_IP_INST(

.refclk (REFCLK),

.rst (RESET),

.outclk_0 (outclk_0),

.outclk_1 (outclk_1),

.zdbfbclk (zdbfbclk),

.locked (locked)

);

endmodule

Regards

Hi,

Assign the zdbfbclk to a pin dedicated for PLL feedback. For example Cyclone V has FPLL_[BL,BR,TL,TR]_FB pins dedicated for this functionality. You can find more details in the Pin Connection Guidelines of the device. Probably the bank 3A for your device does not have this pin. Please check pinout files of your device: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

Recommend you to let the tool assign the pins in first pass and then you can use it as reference.

Regards

Is the requirement mentioned in the handbook fulfilled: "When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee clock alignment at the input and output pins."

Try to assign the input and the zdbfbclk in the same bank and assign same IO standard, in your case 1.5V.

Regards

Hi,

Sorry for the late response. Can you please cross check the pinout files of your target device, whether the allocated pin AC28 is a FPLL_*_FB pin?

Regards