PLL Intel FPGA IP zero delay buffer mode pass at elaboration but failed at compilation

Hi Ash_R_Intel,

I tried out your solution and it works in scale down version of my design. Thanks also for sending me the link to cyclone handbook. the explanation is clear about instantiating zdbfbclk port in top entity to mimic and compensate for clk delay from the CLK output port.

But when i put it on a bigger design, it start to fail for:

Error (169026): Pin zdbfbclk with I/O standard assignment 2.5 V is incompatible with I/O bank 3A. I/O standard 2.5 V, has a VCCIO requirement of 2.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.0V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error.

Correct me if needed : My interpretation of this error is, the zdbfbclk port need a IO-Standard 2.5V. unfortunately, all the IO-Standard in the bigger design is set to IO-Standard 3.3V and 1.5V. No 2.5V.