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Occasional ContributorPLL Intel FPGA IP zero delay buffer mode pass at elaboration but failed at compilation
Hi Ash_R_Intel,
I tried out your solution and it works in scale down version of my design. Thanks also for sending me the link to cyclone handbook. the explanation is clear about instantiating zdbfbclk port in top entity to mimic and compensate for clk delay from the CLK output port.
But when i put it on a bigger design, it start to fail for:
Error (169026): Pin zdbfbclk with I/O standard assignment 2.5 V is incompatible with I/O bank 3A. I/O standard 2.5 V, has a VCCIO requirement of 2.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.0V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error.
Correct me if needed : My interpretation of this error is, the zdbfbclk port need a IO-Standard 2.5V. unfortunately, all the IO-Standard in the bigger design is set to IO-Standard 3.3V and 1.5V. No 2.5V.
Regular ContributorZero-Delay Bu er mode—the PLL feedback path is confined to the dedicated PLL external output pin. The clock port driven o -chip is phase aligned with the clock input for a minimal delay between the clock input and the external clock output.
Also, Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration (intel.com)
You don't have to generate a feedback clock in your code. Need to simply assign zdbfbclk as an inout port in the top module.
Here is the changed code:
module PLL_DRP(
input REFCLK,
input RESET,
output outclk_0,
output outclk_1,
output reg outclk_fb,
inout zdbfbclk,
output reg sel,
output locked
);
always @ (posedge REFCLK)
begin
if(RESET) sel <= 1'b0;
else
begin
if(sel==1'b0) sel <= 1'b1;
if(sel==1'b1) sel <= 1'b0;
end
end
always @ (*)
begin
case (sel)
8'h00 : outclk_fb <= outclk_0;
8'h01 : outclk_fb <= outclk_1;
endcase
end
assign oe = 1'b1;
//assign zdbfbclk = oe ? outclk_fb : 1'bZ;
PLL_DRP_IP PLL_DRP_IP_INST(
.refclk (REFCLK),
.rst (RESET),
.outclk_0 (outclk_0),
.outclk_1 (outclk_1),
.zdbfbclk (zdbfbclk),
.locked (locked)
);
endmodule
Regards
