Forum Discussion
Occasional ContributorPLL Intel FPGA IP zero delay buffer mode pass at elaboration but failed at compilation
Hi Ash_R_Intel,
I tried out your solution and it works in scale down version of my design. Thanks also for sending me the link to cyclone handbook. the explanation is clear about instantiating zdbfbclk port in top entity to mimic and compensate for clk delay from the CLK output port.
But when i put it on a bigger design, it start to fail for:
Error (169026): Pin zdbfbclk with I/O standard assignment 2.5 V is incompatible with I/O bank 3A. I/O standard 2.5 V, has a VCCIO requirement of 2.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.0V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error.
Correct me if needed : My interpretation of this error is, the zdbfbclk port need a IO-Standard 2.5V. unfortunately, all the IO-Standard in the bigger design is set to IO-Standard 3.3V and 1.5V. No 2.5V.
Regular ContributorHi,
Assign the zdbfbclk to a pin dedicated for PLL feedback. For example Cyclone V has FPLL_[BL,BR,TL,TR]_FB pins dedicated for this functionality. You can find more details in the Pin Connection Guidelines of the device. Probably the bank 3A for your device does not have this pin. Please check pinout files of your device: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
Recommend you to let the tool assign the pins in first pass and then you can use it as reference.
Regards
Occasional ContributorHi Ash_R_Intel,
I tried to connect the zdbfbclk port at top entity to the STRATIX V 5SGXA3 series at PIN_AW36(RREF_BL), PIN_AW4(RREF_BR), PIN_B39(RREF_TL) or PIN_B1(RREF_TR), but for some reason, it is giving me Error (171016): Can't place node "zdbfbclk" -- illegal location assignment.
The 2nd alternative i tried was to let the tool assign, and it found a PIN_J16 at bank 7D, which is dedicated for "Other PLL'. But as i compile, it start failing back IO standard 2.5V compatibility issue. After that, i check at the PCBA where the stratix V is placed and found out the bank 7D VCCIO is connected to the 1.5V voltage plane.
unless there is a way to make zdbfbclk port compatible with 1.5V, i don't see a path moving forward.
Many thanks for the advice, learn a lot from this exploration
