Forum Discussion
Occasional ContributorPLL Intel FPGA IP zero delay buffer mode pass at elaboration but failed at compilation
Hi Ash_R_Intel,
I tried out your solution and it works in scale down version of my design. Thanks also for sending me the link to cyclone handbook. the explanation is clear about instantiating zdbfbclk port in top entity to mimic and compensate for clk delay from the CLK output port.
But when i put it on a bigger design, it start to fail for:
Error (169026): Pin zdbfbclk with I/O standard assignment 2.5 V is incompatible with I/O bank 3A. I/O standard 2.5 V, has a VCCIO requirement of 2.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.0V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error.
Correct me if needed : My interpretation of this error is, the zdbfbclk port need a IO-Standard 2.5V. unfortunately, all the IO-Standard in the bigger design is set to IO-Standard 3.3V and 1.5V. No 2.5V.
Regular ContributorIs the requirement mentioned in the handbook fulfilled: "When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee clock alignment at the input and output pins."
Try to assign the input and the zdbfbclk in the same bank and assign same IO standard, in your case 1.5V.
Regards
jkhooHi Ash,
Per your suggestion, i assigned zdbfbclk to the same bank as the input at bank 3B and since in my stratix V PCBA, this bank is source with 3.0V. I also change the IO standard of zdbfbclk to IO-Standard 3.3-V LVCMOS. And this fix the Error (171016): Can't place node "zdbfbclk" -- illegal location assignment.
Now i am facing another error:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter.
Regards, JJ
- jkhoo
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175001): The Fitter cannot place 1 fractional PLL, which is within PLL Intel FPGA IP Pll0.
Info (14596): Information about the failing component(s):
Info (175028): The fractional PLL name(s): PLL_DRP:PLL_DRP_INST|Pll0:PLL_MAIN_INST|Pll0_0002:pll0_inst|altera_pll:altera_pll_i|altera_stratixv_pll:stratixv_pll|altera_stratixv_pll_base:fpll_0|fpll
Error (16234): No legal location could be found out of 12 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): Could not find path between source pin and the fractional PLL
Info (175026): Source: pin zdbfbclk
Info (175015): The I/O pad zdbfbclk is constrained to the location PIN_AC28 due to: User Location Constraints (PIN_AC28)
Info (14709): The constrained I/O pad is contained within this pin
Info (175021): The pin was placed in location AC28
Error (175022): The fractional PLL could not be placed in any location to satisfy its connectivity requirements
Info (175029): 12 locations affected
Info (175029): FRACTIONALPLL_X0_Y1_N0
Info (175029): FRACTIONALPLL_X0_Y10_N0
Info (175029): FRACTIONALPLL_X0_Y91_N0
Info (175029): FRACTIONALPLL_X0_Y100_N0
Info (175029): FRACTIONALPLL_X92_Y2_N0
Info (175029): FRACTIONALPLL_X92_Y11_N0
Info (175029): FRACTIONALPLL_X92_Y87_N0
Info (175029): FRACTIONALPLL_X92_Y96_N0
Info (175029): FRACTIONALPLL_X202_Y1_N0
Info (175029): FRACTIONALPLL_X202_Y10_N0
Info (175029): FRACTIONALPLL_X202_Y91_N0
Info (175029): FRACTIONALPLL_X202_Y100_N0
