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GreenLantern's avatar
GreenLantern
Icon for New Contributor rankNew Contributor
2 years ago
Solved

PLL constraint issues

Getting this hold timing error. Need help resolving it. PLL cross checking found inconsistent PLL clock settings: Clock: i_DAC_TOP|i_PLL|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[...
Timing
  • sstrell's avatar
    sstrell
    2 years ago

    No, you didn't have to break out the PLL output clocks like that. derive_pll_clocks is fine. I was referring to the 3 extra create_clock statements you have (sclk, clk_divider...). Those are coming from internal registers, not an input port of the device, so they should be in your .sdc as create_generated_clock commands, not create_clock.

    As for the failing paths, those look like they are going to Signal Tap, which is debug logic that will be eventually removed. You don't really need to meet timing there.

  • GreenLantern's avatar
    GreenLantern
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hello Nurina,

    I checked the Megawizard options. It doesn't have a "no compensation" mode. I am currently working on a DE10 Standard FPGA with Cyclone V SoC.

    Below is the attached screenshot: