Forum Discussion
New ContributorPLL constraint issues
No, you didn't have to break out the PLL output clocks like that. derive_pll_clocks is fine. I was referring to the 3 extra create_clock statements you have (sclk, clk_divider...). Those are coming from internal registers, not an input port of the device, so they should be in your .sdc as create_generated_clock commands, not create_clock.
As for the failing paths, those look like they are going to Signal Tap, which is debug logic that will be eventually removed. You don't really need to meet timing there.
Super Contributor"master clock period requirement: 0.040" sounds like a .sdc typo. Show the respective constraint.
- GreenLantern
Hello FvM,
I am a little new to this and so the thing is that I am not able to understand which clock is causing this error. The PLL is used to create four clocks:
Reference clock frequency is 25Mhz and Operation Mode is "Direct".
outclk0: 100Mhz
outclk1: 20Mhz
outclk2: 1.63Mhz
outclk3: 150Mhz
I am using a DE10 Standard FPGA which has Cyclone V SoC.
I have attached a screenshot of the sdc file below.
