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Altera_Forum
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16 years ago

PLL compensation delay a minus value?

Hi experts,

I have tested with Altera Quartus tools a design using PLLs and I have read the App note 411. If u have time you can refer to my attachment page 36 line 6. The PLL compensation delay is taken as -2.815. This is not a user specified value and is taken from the device. My question is how come its a minus value and where does this number come from?

I thought PLL compensation means adding delay from the master Clock port to PLL clock in as the clock latency in the generated clock from the PLL.

http://www.altera.com/literature/an/an411.pdf

thanks in advance.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    My question is how come its a minus value and where does this number come from?

    --- Quote End ---

    Hi nilankaraja,

    the minus in -2.815ns means that the edges of the signal to be generated by the PLL has to come 2.815 earlier than the input clock edge.

    Fig 40 in the an411.pdf illustrates a negative offset. (PLL output leading the clock output).

    In a synchronous system all clock edges should occur at the same instance.

    On the FPGA chip there is a special clock network to make sure that all clock edges arrive at flip-flops at (nearly) the same time.

    When going off chip, the delays become much larger and are not under the same control as the balanced on-chip clock network. Therefore the additional delays in the clock signals going off chip have to be taken into account as well as the signal delays.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi sanmao,

    Thanks for the prompt reply.

    So what I gather from you answer is that the PLL of the altera device generates the clock edge 2.815ns earlier that the master clock edge to account for the delay between the PLL out and the Reg clock pin. Am I correct?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    So what I gather from you answer is that the PLL of the altera device generates the clock edge 2.815ns earlier that the master clock edge to account for the delay between the PLL out and the Reg clock pin. Am I correct?

    --- Quote End ---

    You are correct!