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Altera_Forum's avatar
Altera_Forum
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16 years ago

PLL compensation delay a minus value?

Hi experts, I have tested with Altera Quartus tools a design using PLLs and I have read the App note 411. If u have time you can refer to my attachment page 36 line 6. The PLL compensation dela...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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So what I gather from you answer is that the PLL of the altera device generates the clock edge 2.815ns earlier that the master clock edge to account for the delay between the PLL out and the Reg clock pin. Am I correct?

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You are correct!