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My question is how come its a minus value and where does this number come from?
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Hi nilankaraja,
the minus in -2.815ns means that the edges of the signal to be generated by the PLL has to come 2.815 earlier than the input clock edge.
Fig 40 in the an411.pdf illustrates a negative offset. (PLL output leading the clock output).
In a synchronous system all clock edges should occur at the same instance.
On the FPGA chip there is a special clock network to make sure that all clock edges arrive at flip-flops at (nearly) the same time.
When going off chip, the delays become much larger and are not under the same control as the balanced on-chip clock network. Therefore the additional delays in the clock signals going off chip have to be taken into account as well as the signal delays.
Honored Contributor
