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Altera_Forum
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13 years ago

pll clock network delay

I am getting the following clock delays in timing analysis: Roughly 4 ns

in routing clock from PLL to clock input of altsyncram.

I am looking for suggestions on what I am doing wrong here.

How do I get the delay to 0. This path doesn't meet timing for me.

0 1 PLL_L3 altpll_component|auto_generated|pll1|clk[1]

0 RE 4 PLL_L3 PLL

1.224 RE 1 PLL_BUFFER_X0_Y81_N0_I1 PLLBUF

0 RE 1 CLKBUF_IN_X0_Y81_N5_I0 CLKBUF_IN

0 FF IC 1 CLKCTRL_G2 clk~clkctrl|inclk

0.207 FF CELL 2461 CLKCTRL_G2 clk~clkctrl|outclk

0 RE 1 CLKCTRL_G2 TITAN_CLKBUF

0.001 RE 1 CLKBUF_OUT_X0_Y81_N5_I0 CLKBUF_OUT

1.443 RE 15 GLOBAL_CLOCK_X0_Y81_N0_I2 GLOBAL_CLOCK

0.172 RE 22 SPINE_CLOCK_X190_Y122_N0_I11 SPINE_CLOCK

0.153 RE 1 SCLK_TO_ROWCLK_BUF_X190_Y122_N0_I66 SCLK_TO_ROWCLK_BUF

0.043 RE 2 SCLK_TO_ROWCLK_BUF_X190_Y122_N0_I68 SCLK_TO_ROWCLK_BUF

0.2 RE 1 LAB_CLK_X191_Y122_N0_I0 LAB_CLK

0.144 RE 1 BLK_CLK_BUF_X216_Y122_N0_I0 BLK_CLK_BUF

0 FF IC 1 M9K_X216_Y122_N0 mem|auto_generated|ram_block1a0|clk0

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    The text you pasted started at:

    altpll_component|auto_generated|pll1|clk[1]

    Before that, in the timing report, there should be a line item called COMP. In an example I'm looking at, it's a -4ns delay. This is basically the PLL compensating for the clock tree delay by sending a clock out 4ns before the clock coming into the device. (It doesn't actually shift it back, it shifts it forward enough to look like a -4ns shift, but because it's a clock, you can't tell the difference). This is why I asked about the period. For example, if it were 10ns, then if you did a -10ns shift with your PLL, it may look like your timing got better, but you'd be back at where you started. But if it were a 40ns clock, then you could do a -10ns shift and should be fine.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Normal compensation mode is the default for the PLL, and as someone pointed out, it compensates for the delay from the *input clock* to the internal registers. The important thing is that being on a global buffer with high drive, the skew is low between registers, which helps meeting timing for internal register-to-register paths. For I/O timing, you may want to do something different. For source synchronous input timing, you can try Source Synchronous compensation mode, which will maintain the relationship between the input data and the input clock. For output timing, you can try manually adding offset to the output clock in the PLL to adjust your clock skew (with the external capture clock).