pll clock network delay

Normal compensation mode is the default for the PLL, and as someone pointed out, it compensates for the delay from the *input clock* to the internal registers. The important thing is that being on a global buffer with high drive, the skew is low between registers, which helps meeting timing for internal register-to-register paths. For I/O timing, you may want to do something different. For source synchronous input timing, you can try Source Synchronous compensation mode, which will maintain the relationship between the input data and the input clock. For output timing, you can try manually adding offset to the output clock in the PLL to adjust your clock skew (with the external capture clock).