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Altera_Forum
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13 years ago

pll clock network delay

I am getting the following clock delays in timing analysis: Roughly 4 ns in routing clock from PLL to clock input of altsyncram. I am looking for suggestions on what I am doing wrong here. H...
Altera_Forum's avatar
Altera_Forum
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13 years ago

The text you pasted started at:

altpll_component|auto_generated|pll1|clk[1]

Before that, in the timing report, there should be a line item called COMP. In an example I'm looking at, it's a -4ns delay. This is basically the PLL compensating for the clock tree delay by sending a clock out 4ns before the clock coming into the device. (It doesn't actually shift it back, it shifts it forward enough to look like a -4ns shift, but because it's a clock, you can't tell the difference). This is why I asked about the period. For example, if it were 10ns, then if you did a -10ns shift with your PLL, it may look like your timing got better, but you'd be back at where you started. But if it were a 40ns clock, then you could do a -10ns shift and should be fine.