PLL Clock Frequency

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You need to make clock dividers to get lower frequencies.

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If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable. You said you are using a schematic. Choose register primitives that show the clock enable port. Some megafunctions also have a clock enable port available; it might be an option you have to select.

If you drive a lower-speed clock directly from the divide-by-2 register instead of using a clock enable, then it would be best not to have any synchronous paths crossing to or from the divided-down clock domain. In other words, set up the design so that the timing on cross-domain paths does not matter, and use cut-path (false-path) settings to tell Quartus to ignore the timing on the cross-domain paths. (There's also a way to do it with clock settings.) That way the clock skew won't matter for paths that cross between clock domains. Also make sure the divided-down clock is on a global line (you can force this in the Assignment Editor if the Fitter doesn't make the clock global automatically) to minimize clock skew between registers within the domain.

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If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable. You said you are using a schematic. Choose register primitives that show the clock enable port. Some megafunctions also have a clock enable port available; it might be an option you have to select.

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The only megafunction that I could find that had a clock enable was LPM_FF. I'm not sure if this is what you were refering to or not?

Also, I'm using the Cyclone II FPGA.

Thanks.

For register primitives, I meant primitives such as DFFE that have an ENA port. These might be all you need instead of LPM_FF.

For megafunctions, "RAM: 2-PORT" is an example of what I meant. For this particular megafunction, the MegaWizard has a checkbox called "Create one clock enable signal for each clock signal" at "Parameter Settings --> Regs/Clkens/Aclrs". Some megafunctions might have optional clock enables buried behind a "More Options" button.

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If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable.

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Could you explain it in detail ?

Now I am using a PLL in my project to generate a global clock(clk). The frequency of clk is beyond my need. What should to do ?

Divide clk to the new one I need, or change the PLL to a divider to generate my needed clock ?

Thanks.

hapyang

The clock I need is lower than K , so I need a divider to generate the clock, is it ?

In my project , I use some timer to control different domains ,the clocks I use are more than three and the frequencies of which are all under K.

Some suggestions please.

Thanks very much.

If you want to create Freqs with less than 10Megs, I assume that one could do this manually in most cases.

>44MHz, how can I get a 5.5 MHz Clock out"

A Division of 8 might work.

If you observe stability problems, you'll have the change your design to an "enable based" design, reacting on every second clock (and using 11Megs of course).