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Altera_Forum
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18 years ago

PLL Clock Frequency

I'm creating a block schematic and am using LPM_PLL megafunction. The input frequency is 44MHz, but it won't let me create an output frequency lower than 9.3 MHz. Does anyone know how I can ge...
Altera_Forum's avatar
Altera_Forum
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17 years ago

If you want to create Freqs with less than 10Megs, I assume that one could do this manually in most cases.

>44MHz, how can I get a 5.5 MHz Clock out"

A Division of 8 might work.

If you observe stability problems, you'll have the change your design to an "enable based" design, reacting on every second clock (and using 11Megs of course).